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Job ID: 125262415
Skills:
power optimization , C, Linux, Perl, Unix Shell, Tcl, Advanced STA Concepts, Physical Design Flow, Block level PnR convergence, Timing Convergence, Cadence Innovus, LVS, PTSI Tempus, Physical Verification, formal verification, Timing Closure, DRC, PDN, Floor-planning, Place And Route, Synopsys ICC2
Skills:
Scripting, Static Timing Analysis, Routing, Design Compiler, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Extraction, Formal Equivalence, StarRC, Placement, Floor-plan Physical Implementation, RTL to GDS2 flow, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools
Skills:
routing, Scripting Languages, Python, Perl, Tcl, power analysis, primetime, Fusion Compiler, Cadence Innovus, DFT insertion, manufacturing sign-off, Voltus, EDA Tools, low-power design, EM IR analysis, sign-off, advanced nodes, multi-clock domain handling, Synthesis, floorplanning, ASIC SoC physical design flows, Timing Analysis, Physical Verification, reliability checks, Signal Integrity, Timing Closure, Placement, Synopsys ICC2, Clock Tree Synthesis
Skills:
cadence encounter , Unix, Shell, Linux, Flow automation, Synopsys ICC2 tool set, Physical Design, SDC STA, Python Script, PnR tools like ICC2 Innovus, Equivalence checking, Skill
Skills:
Verilog, power analysis, RTL
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