Physical Design Engineer

redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

Scripting, Static Timing Analysis, Routing, Design Compiler, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Synthesis, Formal Equivalence, Extraction, StarRC, Placement, Floor-plan Physical Implementation, RTL to GDS2 flow, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

redhawk , primetime, PDN methodology, floorplanning, physical design implementation, STA constraints, Tempus, Cadence Innovus, IR EM mitigation, Physical Verification, Voltus, signoff tools, Synopsys ICC2

Python Scripting, Routing, Perl, Tcl, Flow Development Automation, Full-chip Physical Design, RTL to GDSII Flow, Signoff, CTS, Advanced Node Experience, floorplanning, STA and Physical Verification

rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, ERC, STA timing closure, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis