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Physical Design Engineer

10-15 Years

This job is no longer accepting applications

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  • Posted 2 months ago

Job Description

  • Lead Netlist to-GDSII implementation, including floorplanning, power planning, placement, CTS, routing, and full signoff (DRC, LVS, STA, EMIR).
  • Own and drive PnR execution and closure at both block and top levels, addressing timing, congestion, IR-drop, and physical verification challenges.
  • Proficient with industry-standard tools: Cadence Innovus, Synopsys ICC2, and scripting in Tcl, Perl, Python for automation and flow development.
  • Deep expertise in low-power design (UPF/CPF), clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe.
  • Collaborate cross-functionally with RTL, STA, DFT, verification, and packaging teams to ensure smooth integration and closure.
  • Manage comprehensive signoff processes, including STA (PrimeTime SI), EM/IR analysis (RedHawk), and physical verification (Calibre); handle ECOs and DRC/LVS clean-up.
  • Provide technical leadership, mentor junior engineers, and contribute to successful tape outs at advanced technology nodes (7nm, 5nm and 3nm

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Job ID: 125262415

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