Physical Design Engineer
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1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation
2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology)
3. Implementation of a project with the full Cadence tools
4. Have worked on complex Hard macros with SerDes and/or critical in timing and area
5. Having experience in Flip-Chip SoC bump Ios)
6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file
SmartSoC Solutions is emerging as a leader in providing engineering solutions worldwide. We offer end-to-end Semiconductor, Embedded, Automotive and System Design to design and build next-generation leadership products under one roof. And allowing clients to achieve both quick wins and long-term results.
Our goal is to be an extended arm of engineering product and IT companies and ensure good quality productization cost-effectively.
Job ID: 113016801
Skills:
DRC LVS clean signoff, Functional and physical ECOs, Placement and optimization, Physical design implementation, floorplanning, Setup hold timing closure, Timing convergence, Power grid design, Routing and post-route optimization
Skills:
Placement and optimization, Timing convergence, Power grid design, Physical design implementation, DRC LVS clean signoff, Automation through scripting, Functional and physical ECOs, Routing and post-route optimization, Methodology improvements, floorplanning, Setup hold timing closure
Skills:
Cadence PVS, IC Validator ICV, ASIC Physical Design flow, CMOS layout concepts, Physical Verification tools, GDSII OASIS formats, advanced technology nodes
