Q
Physical Design Engineer
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Physical Design Engineer
Quess CorpThis job is no longer accepting applications
Job Description
Job Summary
We are looking for a highly skilled Physical Design Engineer to join our VLSI design team. The ideal candidate will have hands-on experience in ASIC physical design implementation from netlist to GDSII, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification. The candidate should possess strong knowledge of advanced technology nodes and industry-standard EDA tools.
Key Responsibilities
- Perform end-to-end physical design implementation from synthesized netlist to GDSII.
- Work on floorplanning, power planning, placement, CTS, routing, and optimization.
- Drive timing closure for setup, hold, and signal integrity violations.
- Perform congestion analysis and optimize design for area, power, and performance.
- Conduct physical verification including DRC, LVS, ERC, and antenna checks.
- Analyze and resolve issues related to IR drop, electromigration (EM), and power integrity.
- Collaborate with RTL, synthesis, STA, DFT, and backend teams for smooth design closure.
- Debug and fix timing, routing, and physical design issues.
- Ensure design meets PPA (Performance, Power, Area) targets.
- Support tapeout activities and signoff closure.
Required Skills
- Strong understanding of ASIC physical design flow.
- Expertise in floorplanning, placement, CTS, routing, and timing closure.
- Good knowledge of STA concepts including setup/hold analysis.
- Experience in low-power design techniques and power optimization.
- Strong understanding of physical verification methodologies.
- Knowledge of signal integrity, IR drop, EM analysis.
- Good scripting skills in Tcl, Perl, Python, or Shell.
- Strong debugging and problem-solving skills.
Required Tools Experience
Hands-on experience in one or more of the following tools:
- Cadence Innovus
- Synopsys ICC2
- Synopsys PrimeTime
- Cadence Tempus
- Mentor Calibre
- RedHawk / Voltus
Note:
Notice Period: Immediate to 30 Days
More Info
Job Type:
Industry:
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Employment Type:
Key Skills
physical verification methodologies
ASIC physical design flow
STA concepts
low-power design techniques
About Company
Skills:
routing, RTL-to-GDS flows, Rtl Design, floorplanning, Physical Verification methodologies, Cadence, LVS, Physical Design, EDA Tools, ERC, Timing Closure, DRC, Placement, Synopsys, Siemens tools, Clock Tree Synthesis
Skills:
Perl, Python, Tcl, UPF, DFT insertion, ATPG, IR-drop analysis, Constraints and SDC, Parasitics, Advanced nodes, Physical Verification, Timing Closure, schematic capture, Placement, Route to sign-off, Low-power implementation, Scan, Floorplan, Layout matching, Multiple power domains, Physical design process, Netlists
Skills:
Python, Tcl, EDA Tools, PrimeClosure, floorplanning, CTS, Innovus, Aspen, Sta, ICC2, IO Timing ECO, Physical Design, Tempus, Postroute Optimization, Seahawk, Placement, Timing Closure, DRC closure, EMIR drop
Skills:
redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus
Skills:
power optimization , routing, Perl, Python, Tcl, physical design flows, floorplanning, digital VLSI concepts, IR-drop, Timing Analysis, Tempus, voltus, Cadence Innovus, LVS, EM analysis, Physical Verification, Rtl Design, EDA Tools, DRC, Placement