Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As a
Physical Design Lead, you will be responsible for driving the complete physical design cycle of high-performance SOCs -- from RTL to final GDSII delivery. This is a leadership role that demands deep technical expertise, strong collaboration across global teams, and a commitment to delivering high-quality silicon on schedule.
You will lead a team of engineers and work closely with cross-functional groups across geo's -- including RTL design, verification, CAD, and integration teams. Your role will be pivotal in shaping the physical design strategy, ensuring design convergence, and maintaining signoff integrity across timing, power, and area metrics.
Minimum Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Principal Duties And Responsibilities:
- Demonstrate proven experience in executing responsibilities across multiple sites.
- Lead and manage a team across multiple spans.
- Exhibit strong analytical and problem-solving skills with a quick learning ability.
- Take complete ownership of PNR implementation, including Floor planning, Placement, CTS, and post-route activities on the latest nodes.
- Possess mandatory signoff knowledge, including STA, Power Analysis, FV, Low Power Verification, and PV.
- Have 12-18 years of experience in Physical Design and timing signoff for high-speed cores.
- Be familiar with high-frequency design convergence for physical design, including PPA targets and PDN methodology.
- Possess over 15+ years of experience in IC design.
- Lead block-level or chip-level Physical Design, STA, and PDN activities.
- Collaborate effectively to resolve issues related to constraints validation, verification, STA, and Physical Design.
- Have knowledge of low power flow, including power gating, multi-Vt flow, and power supply management.
- Understand circuit-level time-critical paths and deep sub-micron design challenges, including leakage power, signal integrity, and DFM.
Minimum Qualifications
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 15+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 13+ years of Hardware Engineering or related work experience.
Preferred Qualifications:
- Good hands-on experience on Floor planning, PNR and STA flows
- Good knowledge of Placement/Clock Tree Synthesis (CTS), Low Power/High Performance optimization, etc.
- Good understanding of signoff domains LEC/CLP/PDN knowledge, etc.
- Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting
- 17+ years Hardware Engineering experience or related work experience.
- 17+ years experience with PNR flow in latest tech nodes (e.g., 3nm/4nm/5nm/7nm)
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