Physical Design Engineer
Physical Design Engineer
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Job Description
Physical Design Engineer – 3+ Years
Job Summary
We are looking for a skilled Physical Design Engineer with 3+ years of experience in RTL-to-GDSII implementation. The candidate should have strong hands-on experience in physical design flows, timing closure, physical verification, and PPA optimization.
Experience
- 3+ years of experience in Physical Design
- Experience in advanced-node technologies is preferred
- Experience with block-level and/or top-level implementation
Key Responsibilities
- Execute the complete RTL-to-GDSII physical design flow.
- Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
- Perform timing analysis and closure using STA.
- Debug and resolve setup/hold violations.
- Optimize designs for Power, Performance, and Area (PPA).
- Perform congestion analysis and optimization.
- Work on clock tree synthesis and clock optimization.
- Analyze and resolve DRC, LVS, antenna, and other physical violations.
- Perform physical ECOs and timing ECOs.
- Work closely with RTL, Synthesis, STA, and PV teams.
- Support block-level integration and tape-out activities.
Most Important Technical Skills
- RTL-to-GDSII Flow
- Floorplanning
- Power Planning
- Placement Optimization
- Clock Tree Synthesis (CTS)
- Routing
- Timing Closure
- Static Timing Analysis (STA)
- Setup/Hold Analysis
- Congestion Optimization
- Physical ECO
- DRC / LVS / Antenna
- IR Drop / EM awareness
- Signal Integrity
- PPA Optimization
- Advanced Node Physical Design
Tools
- Cadence Innovus
- Synopsys ICC2 / Fusion Compiler
- Synopsys PrimeTime
- Cadence Tempus
- Calibre
- RedHawk / Voltus
Education
- B.E./B.Tech/M.E./M.Tech in Electronics & Communication Engineering (ECE), Electrical & Electronics Engineering (EEE), Electronics Engineering, VLSI, or a related field.
- Strong academic background in VLSI, Digital Electronics, CMOS, and Semiconductor Design is preferred.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
RTL-to-GDSII Flow
Clock Tree Synthesis CTS
Physical ECO
IR Drop EM awareness
Placement Optimization
Congestion Optimization
Static Timing Analysis STA
Setup Hold Analysis
Advanced Node Physical Design
PPA Optimization
DRC LVS Antenna
About Company
Skills:
ML optimization tools (DSO.ai), CTS and routing, Timing-driven placement, PPA Optimization, floorplanning, Hierarchical physical design, RTL-to-GDS implementation flow, Synopsys Fusion Compiler, Pin assignment, Timing budgeting
Skills:
Physical Design, Timing Closure, Power Planning, Deep sub-micron technology issues, Floor Planning, Signal integrity analysis, Place And Route
Skills:
Ecos, Perl, Tcl, Python Scripting, Sta, CTS, Cadence Innovus, routing optimization, congestion optimization, SDC, MMMC, advanced technology nodes, full-chip physical implementation, constraint development, floorplanning, PPA improvements, Timing Analysis, setup hold closure, SI crosstalk, Timing Closure, complex SoC designs, Placement, Power Planning
Skills:
Routing, power analysis, Physical Verification, Physical Design, floorplanning, Timing Closure, Placement, DRC, LVS, Signal Integrity, Rtl Design
Skills:
Tcl Scripting, Shell scripting, Python, Routing, Perl, Sta, Signoff, CTS, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Signal Integrity, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2