Experience: 710 years
About the Role
We are seeking a seasoned Physical Design Engineer with deep expertise in advanced-node (7nm) implementation and signoff. You will own end-to-end block/top-level physical designfrom floorplanning to timing closure and physical signoffwithin a high-performance, power-efficient SoC environment. Prior experience with AMD physical design flows and signoff toolchains is highly desirable.
Key Responsibilities
- Block & Top-Level Implementation
- Drive floorplanning, placement, CTS, routing, optimization, and ECO closure for complex IPs/partitions.
- Architect power/clock/domain partitioning and define constraints (SDC) to meet PPA targets.
- Timing & Signoff
- Lead MMMC timing closure across PVT corners and operating modes using advanced methodologies.
- Perform and resolve IR/EM (static & dynamic) issues; manage metal/via strategies for reliability.
- Partner with signoff teams for DRC/LVS closure and systematic yield improvement.
- Analysis & Quality
- Execute CLP/VCLP/FEV analysis to ensure logical/functional equivalence and constraint integrity.
- Evaluate congestion, variation impacts, and implement sub-7nm best practices (e.g., color-aware routing, OCV/AOCV/POCV, useful skew).
- Tool Flow & Automation
- Utilize and tune signoff tools (Fusion Compiler, PrimeTime, RedHawk, Calibre) for high-quality closure.
- Build automation and productivity scripts in Tcl/Perl/Python; contribute to flow enhancements.
- Collaboration
- Work with RTL, DFT, STA, Power, Packaging, and PDN teams to converge on schedule and quality.
- Support silicon bring-up with physical-design insights and post-silicon feedback loops.
Required Qualifications
- 7+ years of hands-on ASIC/SOC physical design at advanced nodes (preferably 7nm/5nm or below).
- Strong expertise across floorplanning, placement, CTS, routing, ECOs, and MMMC timing closure.
- Proven experience in IR/EM analysis, CLP/VCLP/FEV checks, and power/clock/domain partitioning.
- Proficiency with signoff tools: Synopsys Fusion Compiler, PrimeTime, Ansys RedHawk, Mentor/Siemens Calibre (or equivalent).
- Scripting skills in Tcl, Perl, Python for flow automation and data analysis.
- Deep understanding of sub-7nm challenges: congestion management, variability (AOCV/POCV), advanced CTS/clocking, and EM-aware design.
Nice-to-Have
- Exposure to AMD-specific physical design flows and signoff methodologies.
- Experience with UPF/CPF low-power implementation and verification.
- Knowledge of DFT-aware physical implementation, hierarchical timing signoff, and top-level integration.
- Familiarity with chip/package co-design, thermal-aware analysis, and advanced PDN techniques.
- Experience guiding junior engineers and conducting design reviews.
Education
- B.E./B.Tech or M.E./M.Tech in Electrical/Electronics/Computer Engineering (or related).
Tools & Technologies (Representative)
- Implementation/STA: Synopsys Fusion Compiler, IC Compiler II, PrimeTime
- IR/EM & Power: Ansys RedHawk (FX/SC), Voltus (if applicable)
- Physical Verification: Calibre DRC/LVS/DRC+, PERC
- Scripting: Tcl, Perl, Python
- Version Control & CI: Git/Perforce; Jenkins (nice-to-have)
