Physical Design and Timing Signoff Methodology, Silicon

Responsibilities

• Drive the physical design and sign-off timing methodologies for mobile System on a Chips (SoC) to push PPA and yield.
• Analyze power performance area trade-offs across different methodologies and technologies.
• Work with cross-functional architecture, IPs, design, foundry, CAD and sign-off methodology teams.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience in timing analysis and physical design.
• Experience in one or more scripting languages, such as Perl, Tcl, Python.

Preferred qualifications:

• Experience in physical design tool automation: synthesis, PandR tools.
• Experience in extraction of design parameters, QoR metrics and analyzing data trends.
• Experience in engineering across physical design and level implementation.
• Knowledge of timing signoff conditions and parameters.
• Understanding of parasitic extraction tools and flow.