Experience: Trained in Physical Design / STA / DFT / Physical Verification; 1-3 years of Industry exposure, Training experience preferred
Type: Full-Time, Immediate Requirement
Job Description:
Ramaiah Academy is looking for an experienced professional in Physical Design & Verification. The candidate will train students and working professionals on industry-standard RTL-to-GDSII flow, Static Timing Analysis, Low Power Design, DFT, and Physical Verification using leading EDA tools like Cadence or Synopsys.
Roles & Responsibilities:
- Develop high-quality content, assignments, and assessments
- Deliver classroom/online training on ASIC Physical Design flow (Synthesis to Signoff)
- Guide the application of advanced Static Timing Analysis, UPF-based low-power design principles, and parasitic extraction techniques to enhance circuit performance
- Deliver in-depth training on DFT methodologies, including Scan Chain Insertion, ATPG generation, Fault Modelling, and BIST architecture implementation
- Guide learners on Physical Verification flows DRC, LVS, Antenna, ERC
- Mentor for real-time projects, interview preparation, and tool labs
Skill Requirements:
- Hands-on experience in Physical Design tools (Cadence Innovus, Synopsys ICC2, PrimeTime)
- Practical understanding of FINFET/CFET, advanced nodes (7nm/5nm/3nm), and layout effects (WPE, LOD)
- Working knowledge of DFT and STA fundamentals
- Prior training/mentoring experience preferred
- Effective communication and presentation skills
