PAGLS / PARTL Verification Engineer

PAGLS / PARTL Verification Engineer

Job Responsibilities

• Responsible for building GLS environment (Unit delay & Timing) setup.

• Bring up sanity simulations across cores with Unit delay & Timing simulations.

• Work with Architecture and Design teams to understand low-power design features and create verification plans.

• Develop verification components and testbench for low-power verification and integrate third-party VIPs/UVCs as required.

• Create constraint-random verification environment using SystemVerilog and UVM.

• Perform Power Aware Verification in a random verification environment on the design.

• Regress and close required Low Power coverage metrics to ensure high-quality design.

Minimum Skills

• 8+ years of Design Verification experience.

• Bachelor's degree in science, Engineering or closely related field.

• 3+ years hands-on experience in SystemVerilog, OVM/UVM-based constrained-random verification.

• 3+ years hands-on experience developing GLS environment, GATE ID creation, verification components/UVCs and testbench for GLS verification.

• 3+ years hands-on testbench bring-up, integrating third-party VIPs, digital design, verification, debugging and waveform debug.

• 2+ years of experience in UPF-based Power Aware verification.

• 2+ years of experience in functional coverage model development and/or code coverage closure.

• Proficient with low-power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.

• Strong communication skills to interact with a global team.

Desirable

• BE/ME degree in Electrical Engineering or equivalent.

• Experience with Synopsys NLP (native Low Power) tool.

• Working knowledge of GLS, PAGLS and scripting languages such as Perl/Python is a plus.

• Worked on Low Power coverage metrics collection and coverage closure.

• Post-Silicon debug experience.

• Knowledge of GPU/CPU/DDR/Bus preferred.

• Formal verification experience and/or Low Power Formal Verification experience.