THE ROLE:
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Responsible for prototyping SOC design for emulators/FPGAs and running pre-Si tests
- Work on one or more of the emulators or FPGA solutions - Palladium/ZeBu/Veloce/Protium
- Work with SOC DV stakeholders to put all the design/programming pieces together
- Build and deliver qualified emulation/FPGA models to pre-Si validation teams
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC verification
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Graphics pipeline knowledge
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux with exposure to Windows platform
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Good working knowledge of SystemC and TLM with some related experience.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assets with prior exposure to video codec system or other multimedia solutions.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
