MTS Silicon Design Engineer

A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Work on full chip IR/EM convergence on multiple ASICs across different technology nodes.
• Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design.
• Work with RTL and PD team in coming up with the low power and UPF specification for the SoC.
• Work closely with CAD team to come up with new flows and methodologies in the power integrity domain.

PREFERRED SKILLSET:

• 6+ years of professional experience in the industry in power integrity domains
• Good knowledge of Power delivery and power integrity flows
• Hands on experience on industry standard tools especially Redhawk based power integrity analysis
• Good in scripting languages such as Tcl and Perl
• Self driven, positive attitude and team worker