Job Description
We are looking for an experienced Memory Layout Engineer with 3 to 6 years of experience for immediate joining. The candidate will be responsible for custom memory layout design, physical verification, and layout optimization for high-density and low-power memory blocks.
Roles & Responsibilities
- Design and develop SRAM/Memory layouts from schematic.
- Work on Memory Arrays, Column I/O, Decoders, Control Blocks, and related circuits.
- Perform DRC, LVS, XOR, and physical verification checks.
- Resolve layout issues related to shorts, opens, antenna, latch-up, and density.
- Ensure layout quality, symmetry, matching, and routing optimization.
- Collaborate with circuit designers and verification teams.
- Execute layout reviews and documentation activities.
Required Skills
- 3 to 6 years of experience in Memory Layout Design.
- Good understanding of SRAM architecture and custom layout concepts.
- Knowledge of EM, IR Drop, Crosstalk, Antenna, ESD, and Latch-up effects.
- Hands-on experience with Cadence Virtuoso, Calibre, PVS, or similar EDA tools.
- Experience in FinFET technology is preferred.
- Strong debugging skills for DRC/LVS issues.
Qualification
- Bachelor's or Master's degree in Electronics/ECE/VLSI or related field.
- Immediate joiners are highly preferred.
