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Capgemini Engineering

Memory Layout Engineer

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Job Description

Role: Memory/Custom Layout Engineer

Experience: 3 to 12 Years

Location: Bengaluru

Job Description:

  • 3-8 years of experience in Memory/Custom Layout design.
  • Memory Leafcell layout library design from scratch including top level integration.
  • Good knowledge on different types of memory architectures.
  • Good knowledge in optimized layout design for better performance.
  • Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.
  • Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
  • Good Knowledge in EM and IR run and fix.
  • Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow

Primary Skills:

  • Memory leafcell layout library design from scratch, including top-level integration.
  • Strong understanding of various memory architectures.
  • Expertise in optimized layout design for enhanced performance.
  • Hands-on experience with FinFET technology, layout design, and DRC limitations.
  • Proficiency in Cadence Virtuoso layout editor.
  • Proficient in Calibre physical verification flow.

Secondary Skills:

  • Good knowledge of physical verification flows and debugging (DRC, LVS, ERC, boundary conditions).
  • Familiarity with EM and IR analysis, including run and fix processes.

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About Company

Job ID: 130479849

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