Responsibilities:
- Implementation of quality full-custom layouts of high-performance arrays and memory blocks from supplied schematics: from planning stages through final layout verification and review, in accordance with strict guidelines for performance and manufacturability.
- Must have experience with Cadence Virtuoso layout systems.
- Resource for interpretation and implementation of all physical design rules in the most advanced manufacturing processes used by ARM.
- Custom layout and verification of complex memory cells.
- Expert physical design verification (DRC/LVS/DFM) resource for all types of circuit and test layouts using Calibre verification tools.
Required Skills and Experience :
- The ideal candidate is expected to have 3+ years pertinent layout design experience. With a Bachelors/Masters or equivalent with minimum of 3+ years of work experience in layout development
- Ability to understand, plan and organize work using complex schematics of hierarchically structured circuits.
- Understanding of layout techniques for optimization of power, speed, and area for data path, bitcell arrays, word line drivers, control blocks, and other complex memory circuits.
- Ability to quickly interpret and repair complicated LVS and DRC problems using state of the art verification software.
- Ability to accurately plan and schedule responsibilities.
Nice To Have Skills and Experience :
- Understanding layout techniques for design-for-manufacture in advanced (7nm/5nm/3nm/2nm) processes.
- Ability to identify possible design tradeoffs with circuit design leads, based upon assumptions, inherent knowledge, and design analysis.
- Programming experience: Tcl, Perl, shell, Skill, Scheme.
