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Position: Lead Verification Engineer -Applied ML - Functional Verification
About Us
Position Overview
We are seeking results driven Pre-Silicon Verification Engineer with extensive experience in function verification (formal verification and/or simulation/UVM verification) and a passion for leveraging artificial intelligence to redefine the verification landscape. In this role, you will operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI tools to architect, design, and validate the next generation of verification methodologies. You will collaborate closely with a highly skilled team of machine learning engineers experienced in training large language models on a scale, as well as accomplished software engineers with proven expertise in product development and deployment.
Key Responsibilities
Required Qualifications
The Cadence Advantage
Cadence is a health technology company helping the nation’s most patient-centric health systems deliver more consistent, proactive healthcare every day. Cadence’s remote patient intervention solution couples powerful new technology with clinical excellence, providing its patients a precise and personal level of care all outside of the four walls of the hospital.At Cadence, we aim to exceed the expectations of our patients, clinicians, and partners every day. Our team values trust and autonomy, and we empower one another to make decisions, solve problems and build something better. We give clear, candid feedback with the utmost honesty and encouragement. If you’re interested in joining us, explore opportunities at www.cadence.care.
Job ID: 144103619
Skills:
Machine Learning, Rft, Verilog, System Verilog, Python, Uvm, LLMs, Pre-Silicon Verification, EDA Tools, Agentic frameworks, formal verification, RAG, RL
Skills:
Jtag, Verilog, Embedded Firmware, System Verilog, Power management verification, MBIST, Formal verification methodologies, IEEE1500, UPF, C Language, Hardware, Dft
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