Lead Software Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Lead Software Engineer - Virtual & Hybrid Platforms

About the Role

At Cadence Design Systems, Virtual and Hybrid Platforms are the foundation that lets software teams get to work months before silicon arrives. The Lead Software Engineer in this role will own that foundation, from ROM and early boot through Linux/Android bring-up, and directly shape how Cadence's SoC software ecosystem comes to life.

The candidate will work at the intersection of hardware and software, influence architecture decisions early in the design cycle, and mentor engineers solving some of the hardest bring-up and co-debug challenges in the industry. This role is designed for engineers who thrive at the hardware/software boundary and want their work to have multiplied impact across every team that depends on early platform readiness.

Key Responsibilities

• Develop and integrate Virtual and Hybrid Platforms using SystemC/TLM and RTL components, enabling early and continuous software development well ahead of silicon availability.
• Lead end-to-end platform readiness from early boot (ROM, bootloaders, firmware) through OS bring-up and stability, serving as the go-to technical owner for platform health across the program.
• Debug complex HW/SW issues using waveform analysis, GDB, JTAG, and co-debug methodologies, driving issues to root cause with rigor and depth.
• Serve as a connective technical force across architecture, RTL, IP, firmware, validation, and customer teams, translating hardware intent into software reality.
• Drive platform performance optimization, multi-threading enablement, and deadlock analysis to ensure platform stability at scale.
• Apply AI-assisted tools and workflows to accelerate development, debugging, log analysis, bring-up automation, and overall team productivity.

Required Qualifications

• 5+ years of software development experience, with meaningful depth in pre-silicon or SoC platform environments.
• Strong proficiency in C++, SystemC, and TLM 2.0.
• Hands-on experience developing and integrating SoC Virtual Platforms and Hybrid Platforms.
• Proven experience integrating RTL with virtual or emulation environments.
• Strong understanding of SoC architecture, system-level design, and hardware/software interactions.
• Expertise in software debugging, waveform-based debug, and HW/SW co-debug across complex systems.
• Solid programming and scripting skills across C/C++, Python, and Shell.
• Hands-on experience with multi-threaded software, synchronization, concurrency challenges, and deadlock analysis.
• Hands-on experience with Linux and/or Android bring-up, including boot flow debugging, kernel bring-up, and OS stability analysis.

Preferred Qualifications

• Experience with Arm-based SoCs, AMBA protocols, and emulation platforms.
• Familiarity with QEMU, Fast Models, or processor simulation environments.
• Experience working in a pre-silicon environment where virtual platforms are the primary software development vehicle.
• Comfort with AI-assisted development, debugging, and automation workflows.

Why Cadence

• Early Impact. The candidate will not be integrating someone else's decisions they will be making them. Platform work at this level directly unblocks software development across multiple teams and product lines at Cadence.
• Hard Problems. Pre-silicon HW/SW co-debug at scale is genuinely difficult, and this team operates at the leading edge of that space.
• Cross-Functional Reach. The candidate will work closely with architecture, RTL, and firmware teams, not as a downstream consumer, but as a peer shaping how the platform evolves.
• Technical Leadership That Means Something. This is a role with real ownership, real mentorship responsibility, and a direct line to product outcomes at one of the semiconductor industry's most respected EDA and IP companies.

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