Lead SOC Design Verification/Emulation Engineer

Lead SOC Design Verification/Emulation Engineer Candidate Qualifications

Minimum qualifications:

•Bachelor's degree in electrical engineering or computer science

•Verilog/System Verilog based verification experience at Subsystem and Full chiplevel.

Preferred qualifications:

•Bachelor's degree in Electronics Engineering or Computer Science with 7 - 12 years of relevant experience, or master's degree in Electronics Engineering or Computer Science with 7 - 10 years of relevant experience.

•Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols.

•Experience with System Verilog Assertions with industry standard tools a plus

•Experience with SOC boot flow, clocking and platform bring up in Emulators or Silicon desired

•Experience with Low Power Verification and power management flows.

•Experience with RTL, GLS level simulations, Co-Simulations

•Experience working on PCIE/USB/Ethernet and other HSIO desired

•Experienced in UVM based Methodology Development.

Roles & Responsibilities:

•Be part of a team to verify complex system on a chip designs. Interact with designengineers to identify important verification scenarios.

•Create and enhance constrained-random verification environments using UVM/SystemVerilog

•Create complex C/SV tests using reusable test libs.

•Team player and a mentor who is self-driven, motivated and guides a team of juniorengineers

•Responsible for quality and timeliness of the team outputEmail

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