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Lead RTL Design Engineer

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  • Posted 12 hours ago
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Job Description



WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.




MTS SILICON DESIGN ENGINEER

THE ROLE:

The focus of this role is to plan, build, and execute the design and validation of new and existing features for AMD's DDR IPs.

THE PERSON:

We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of AMD-Xilinx FPGA Architecture. In this role, you will design Register-Transfer Level (RTL) Intellectual Property (IP) with a focus on High Speed IO Connectivity subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the IO based connectivity systems. You will be also responsible for RTL coding of blocks specified by you or others. Additionally, you will be responsible for various front-end methodology flows that include resource optimization, clock domain crossing and reset domain crossing.

Qualifications:

  • Strong knowledge of system-level architecture including buses like AXI, bridges, memory controllers , High Speed serial connectivity, etc
  • Strong in digital design, micro architecture , RTL development
  • Strong in VHDL/Verilog, System C, system debug, timing analysis
  • Hands on experience with AMD/Xilinx FPGA device and Vivado toolchain.
  • Hands on experience with architecting / micro-architecture / detailed design from functional specifications.
  • Lint, CDC, synthesis flow and static timing flows, formal checking, etc. experience.
  • Working knowledge / experience C++, TCL, Perl, Python is required
  • Has a solid desire to learn and explore new technologies.
  • Ability to develop longer-range project plans and schedules to complete complex projects or new product development.
  • Ability to effectively communicate with customers about existing and new product directions and technology.
  • Strong communication and presentation skills.
  • Close collaboration with different teams across various time zones.

ACADEMIC CREDENTIALS:

  • Bachelor's or Master's degree in computer engineering/Electrical/Electronic Engineering with 8+ years of exp

#LI-SR4




Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available

This posting is for an existing vacancy.

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About Company

Xilinx, Inc. was an American technology and semiconductor company that primarily supplied programmable logic devices. The company was known for inventing the first commercially viable field-programmable gate array and creating the first fabless manufacturing model.

Job ID: 139066655

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