Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies

Lead RTL design Engineer

Inotec AMD

8-10 yrs

Bengaluru, India

Skills:

Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies

RTL(IP) Design Engineer/Infra - Sr Lead/Staff

Qualcomm

8-10 yrs

Bengaluru, India

Skills:

rtl development , virtualization, Clp, LINT, DFT verification, cdc, IP SoC design, silicon debug, SoC Design Verilog RTL coding, PLDRC, formal verification, coherency protocols, micro-architecture, Digital Design

RTL ASIC Front end Design Engineer/ Lead - INDIA

Tessolve

5-10 yrs

Bengaluru, India

Skills:

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture