Role: Physical Design Engineer (EMIR)
Bangalore, Hyderabad, Pune & Ahmedabad
About Company:
About
We are a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. Our success is anchored in the unparalleled expertise of our engineering leadership team, whose collective experience spans renowned tech giants like Google, Cisco, Microsoft, Oracle, Uber, Broadcom, and Sun. With a commitment to innovation and excellence, we deliver cutting edge solutions that empower businesses to thrive in the ever-evolving digital landscape.
Experience: 8 to 14 years
Location: Bangalore, Hyderabad, Pune & Ahmedabad
Role: Physical Design Engineer (EMIR)
Experience: 8 to 14 years
Location: Bangalore, Hyderabad, Pune & Ahmedabad
Job Description :
We are seeking an exceptional Fullchip/SS Power EM/IR Lead to take a key role in our semiconductor design team. As a Power EM/IR Lead, you will lead the PDN closure of cutting-edge complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs.
Responsibilities:
- Develop the flow, scripts & perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, in-rush-current/powerup analysis and ESD.
- Drive block and top-level power closure
- Develop static/dynamic IR, power/signal EM, ESD and power grid specs based on power/performance/area targets of different SOC blocks.
- Implement power grids in industry standard PnR tool environments
- Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks.
- Work closely with the Package and/or Power Integrity teams to optimize the overall PDN performance.
- Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence.
- Work closely with PD teams to understand design requirements and constraints, and drive successful tapout of designs.
- Support and Development of advanced methodologies and flows for complex semiconductor designs.
Requirements:
- Bachelor's or Master's degree in Electrical Engineering or Electronics & Communications.
- Proficiency in industry-standard EDA tools Redhawk, Voltus etc.
- Experience in developing and implementing power grid for advance node.
- Good knowledge of system-level PDN and power integrity at each development stage.
- Working knowledge of PnR implementation, verification, power analysis and STA.
- Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.
- Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule.
- Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment.
Preferred qualifications:
- Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology.
- Has at least worked on power for 2 full chip implementation of large size silicon.
- Experience in handling Partitions and blocks for PDN closure.
- Has worked on PDN Flow part for Redhawk, Voltus and other tools.
- Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration.
- Experience and good understanding in various foundries and their Backend implementation requirement.
Contact
Uday
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Mulya Technologies
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