Lead Physical Design Engineer
Location-Bengaluru
About the Role
We are looking for a Lead Physical Design Engineer with deep technical expertise in electromigration (EM), IR drop analysis, and reliability signoff flows. This role is highly technical, focused on driving robust power integrity and reliability closure for advanced SoCs. You will be handson with industryleading tools, methodologies, and flows, ensuring silicon meets stringent performance, power, and reliability targets.
Responsibilities
- Core Technical Execution
- Own EM/IR analysis and signoff for complex SoCs across advanced technology nodes (7nm, 5nm, or below).
- Perform power grid design, analysis, and optimization to ensure robust IR drop margins.
- Conduct electromigration checks, current density analysis, and reliability verification.
- Drive static/dynamic IR drop simulations and correlate with silicon measurements.
- Collaborate with RTL, floorplanning, and power architects to optimize power delivery networks (PDN).
- Develop methodologies for early EM/IR prediction and prevention during design stages.
- Automate EM/IR flows using scripting (Tcl, Python, Perl) to improve efficiency and accuracy.
- CrossFunctional Collaboration
- Partner with physical design, timing, and verification teams to ensure reliability closure aligns with PPA goals.
- Interface with EDA vendors to evaluate and deploy advanced EM/IR analysis tools and methodologies.
- Provide technical guidance to junior engineers on EM/IR best practices and tool usage.
Basic Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- 5–10 years of handson experience in physical design with a strong focus on EM/IR analysis.
- Expertise in industrystandard tools (Ansys RedHawk, Cadence Voltus, Synopsys PrimePower/PrimeRail).
- Solid understanding of power grid design, current density, and reliability verification methodologies.
- Experience with advanced technology nodes (7nm, 5nm, or below).
- Strong scripting skills (Tcl, Python, Perl) for flow automation.
Preferred Qualifications
- Proven track record of EM/IR closure on largescale SoCs.
- Familiarity with dynamic voltage drop analysis and correlation with silicon bringup.
- Knowledge of lowpower design techniques, multivoltage domains, and power gating.
- Exposure to highperformance CPU/GPU/AI accelerator designs.
- Ability to mentor and technically lead small teams in reliability closure.
