Lead Physical Design Engineer

Job Title: Lead Physical Design Engineer

Company: ACL Digital

Location: Chennai

Experience: 8+ Years

Industry: Semiconductor / VLSI Design

Job Summary:

We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design flow. The ideal candidate should have deep knowledge of implementation using Cadence Innovus and be capable of handling complex SoC blocks independently.

Key Responsibilities:

• Perform full-chip/block-level physical design activities including:
• Floorplanning
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• Physical Verification
• Work extensively with Cadence Innovus for implementation and optimization
• Drive timing closure, congestion analysis, and power optimization
• Handle IR drop, EM analysis, and physical signoff checks
• Collaborate with RTL, DFT, STA, and verification teams
• Debug and resolve DRC/LVS issues and ensure clean tapeout
• Work on advanced technology nodes (e.g., 7nm, 5nm is a plus)

Required Skills:

• Strong expertise in Physical Design flow from Netlist to GDSII
• Hands-on experience with:
• Cadence Innovus
• Timing analysis tools like Synopsys PrimeTime
• Solid understanding of:
• Timing closure (setup/hold fixing)
• Signal integrity and noise analysis
• Low power techniques
• Experience with scripting (TCL, Shell, Python is a plus)
• Good debugging and problem-solving skills