Lead Engineer
- Posted a month ago
- Be among the first 10 applicants
Job Description
Job Requirements
At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Key Responsibilities
Full-Stack Physical Design: Owning the RTL-to-GDSII flow, including physical-aware synthesis, floor planning, placement, routing, and clock tree synthesis (CTS).
3D-IC and Signoff Execution: Working on 3D heterogeneous integration and multi-die assemblies, managing TSV (Through-Silicon Via) planning, IR drop, electro-migration (EM), and static timing analysis (STA).
Power & Performance: Focusing on low-power implementation using UPF/CPF and strict timing closure for high-frequency designs (>1GHz).
Methodology Development: Collaborating with IP/foundry partners and developing automation scripts in Tcl, Python, or Perl.
Experience: 5+ to 10+ years of hands-on ASIC/SoC Physical Design experience with multiple full-cycle tape-outs at advanced nodes (5nm, 3nm, or 2nm).
Domain Expertise: Solid understanding of multi-corner multi-mode (MMCM), signal integrity, and 3D packaging technologies.
Tool Proficiency: Deep experience with industry-standard EDA tools like Cadence (Innovus, Tempus, Voltus) or Synopsys (ICC2, PrimeTime).
Scripting Skills: Proficiency in Tcl (mandatory), Python, or Perl
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.
Work Experience
Required Skills:
Full-Stack Physical Design: Owning the RTL-to-GDSII flow, including physical-aware synthesis, floor planning, placement, routing, and clock tree synthesis (CTS).
3D-IC and Signoff Execution: Working on 3D heterogeneous integration and multi-die assemblies, managing TSV (Through-Silicon Via) planning, IR drop, electro-migration (EM), and static timing analysis (STA).
Power & Performance: Focusing on low-power implementation using UPF/CPF and strict timing closure for high-frequency designs (>1GHz).
Methodology Development: Collaborating with IP/foundry partners and developing automation scripts in Tcl, Python, or Perl.
Experience: 5+ to 10+ years of hands-on ASIC/SoC Physical Design experience with multiple full-cycle tape-outs at advanced nodes (5nm, 3nm, or 2nm).
Domain Expertise: Solid understanding of multi-corner multi-mode (MMCM), signal integrity, and 3D packaging technologies.
Tool Proficiency: Deep experience with industry-standard EDA tools like Cadence (Innovus, Tempus, Voltus) or Synopsys (ICC2, PrimeTime).
Scripting Skills: Proficiency in Tcl (mandatory), Python, or Perl
At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Key Responsibilities
Full-Stack Physical Design: Owning the RTL-to-GDSII flow, including physical-aware synthesis, floor planning, placement, routing, and clock tree synthesis (CTS).
3D-IC and Signoff Execution: Working on 3D heterogeneous integration and multi-die assemblies, managing TSV (Through-Silicon Via) planning, IR drop, electro-migration (EM), and static timing analysis (STA).
Power & Performance: Focusing on low-power implementation using UPF/CPF and strict timing closure for high-frequency designs (>1GHz).
Methodology Development: Collaborating with IP/foundry partners and developing automation scripts in Tcl, Python, or Perl.
Experience: 5+ to 10+ years of hands-on ASIC/SoC Physical Design experience with multiple full-cycle tape-outs at advanced nodes (5nm, 3nm, or 2nm).
Domain Expertise: Solid understanding of multi-corner multi-mode (MMCM), signal integrity, and 3D packaging technologies.
Tool Proficiency: Deep experience with industry-standard EDA tools like Cadence (Innovus, Tempus, Voltus) or Synopsys (ICC2, PrimeTime).
Scripting Skills: Proficiency in Tcl (mandatory), Python, or Perl
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.
Work Experience
Required Skills:
Full-Stack Physical Design: Owning the RTL-to-GDSII flow, including physical-aware synthesis, floor planning, placement, routing, and clock tree synthesis (CTS).
3D-IC and Signoff Execution: Working on 3D heterogeneous integration and multi-die assemblies, managing TSV (Through-Silicon Via) planning, IR drop, electro-migration (EM), and static timing analysis (STA).
Power & Performance: Focusing on low-power implementation using UPF/CPF and strict timing closure for high-frequency designs (>1GHz).
Methodology Development: Collaborating with IP/foundry partners and developing automation scripts in Tcl, Python, or Perl.
Experience: 5+ to 10+ years of hands-on ASIC/SoC Physical Design experience with multiple full-cycle tape-outs at advanced nodes (5nm, 3nm, or 2nm).
Domain Expertise: Solid understanding of multi-corner multi-mode (MMCM), signal integrity, and 3D packaging technologies.
Tool Proficiency: Deep experience with industry-standard EDA tools like Cadence (Innovus, Tempus, Voltus) or Synopsys (ICC2, PrimeTime).
Scripting Skills: Proficiency in Tcl (mandatory), Python, or Perl
More Info
Key Skills
IR drop
Tempus
Cadence Innovus
UPF
3D heterogeneous integration
Voltus
RTL-to-GDSII flow
Synopsys ICC2
low-power implementation
multi-die assemblies
physical-aware synthesis
About Company
Skills:
Silicon Validation, Shell, Perl, automation, Python, Scripting, power analysis, Emulation, Simulation, performance models, power models, power estimation tools, NSP architectures
Skills:
Python, Excel Vba, ANSYS-Classic Workbench, Lean Principles, Nx, AI-driven tools
Skills:
Django, Machine Learning, Microsoft Azure, Django Rest Framework, Automated Testing, Python, Kubernetes, generative AI, SRE principles, observability
Skills:
Python, System Verilog, Systemc, Pcie, Hybrid test benches, MDV, DV signoffs, SV, CDV, Uvm, Simulation Scripts, test vectors, Coverage, Regression, UCIe, Axi, testplan creation, DV Infrastructure, building testbenches, stimulus based verification, SystemC based reference model
Skills:
Static Timing Analysis, Constraints, Timing Closure, industry-standard STA tools