Lead DFT Engineer
Lead DFT Engineer
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Job Description
Lead DFT Engineer
Location: Bengaluru, India
Experience: 6–12 Years
What You'll Do
- Drive end-to-end Design-for-Test (DFT) architecture and implementation for complex SoC and subsystem designs.
- Define and implement Scan, Scan Compression, ATPG, MBIST, Boundary Scan (JTAG), and Logic BIST solutions.
- Develop DFT architecture aligned with product quality, test coverage, power, and manufacturing requirements.
- Own DFT insertion, pattern generation, pattern validation, and sign-off across multiple IPs and full-chip integration.
- Debug DFT-related issues during RTL, gate-level simulation, emulation, and post-silicon bring-up.
- Collaborate with RTL, Physical Design, STA, Verification, and Product Engineering teams to ensure seamless test integration.
- Analyze coverage, diagnose pattern failures, optimize ATPG runtime, reduce test time, and improve silicon yield.
- Drive DFT closure for advanced technology nodes while meeting aggressive schedule and quality targets.
What We're Looking For
- 6–12 years of hands-on experience in ASIC/SoC DFT.
- Strong expertise in Scan Architecture, Scan Compression, ATPG, MBIST, Boundary Scan (IEEE 1149.1), and Logic BIST.
- Deep understanding of stuck-at, transition, path-delay, bridge, and cell-aware fault models.
- Experience with hierarchical DFT methodologies and large SoC integration.
- Strong debugging skills in GLS, SDF simulations, tester pattern validation, and silicon failure analysis.
- Proficiency in Verilog/SystemVerilog and scripting using Tcl, Perl, Python, or Shell.
- Good understanding of clocking, reset architecture, low-power design (UPF/CPF), and DFT-aware implementation.
- Hands-on experience with industry-standard DFT EDA tools such as Synopsys TestMAX/DFT Compiler or Siemens Tessent.
- Familiarity with STA, synthesis, Physical Design, and manufacturing test flows is highly desirable.
Preferred Qualifications
- Experience with advanced nodes (7nm/5nm/3nm or below).
- Exposure to IEEE 1500, IEEE 1687 (IJTAG), OCC, EDT, and X-bounding methodologies.
- Experience supporting ATE bring-up, silicon debug, and yield improvement.
- Ability to technically lead projects, mentor engineers, and drive DFT execution independently across multiple tape-outs.
More Info
Job Type:
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Key Skills
Siemens Tessent
Synopsys TestMAX
DFT EDA tools
Scan Architecture
Scan Compression
IEEE 1149.1
Shell
About Company
Skills:
bist , boundary scan , Jtag, test compression, ATPG, EDA Tools, Scan Insertion, DFT methodologies, Logic Memory, Synopsys TestMAX, Mentor Tessent
Skills:
MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification, Mentor Cadence Synopsys Tools
Skills:
Perl, Shell scripting, Scan Insertion, Stuck at Transition ATPG, silicon debug, DFT Silicon bring up expertise, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Synopsys Tetramax, SOC Tape-Outs, Verilog RTL design, DFTMAX, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
Skills:
scan compression, DFT architecture, ATPG, Scan Insertion, MBIST, Cadence DFT tools, test coverage analysis
Skills:
Dft, ATPG, MBIST, CCS JTAG