Lead IP/SoC Verification Engineer PCIe Gen6
Location: Bengaluru, India
Experience: 612 Years
About the Role
We are seeking an experienced Lead Verification Engineer with deep expertise in PCI Express (PCIe) Gen6 IP and SoC-level verification. The ideal candidate will drive verification strategy, architecture, execution, and closure for next-generation high-performance designs, while mentoring teams and collaborating with cross-functional groups (architecture, RTL design, validation, PD).
Technical Leadership
- Own verification architecture, methodology, and testbench design for PCIe Gen6 IP/Subsystem/SoC integration.
- Define and implement verification strategies, including test plans, coverage models, and metrics.
- Lead verification cycles from environment bring-up to coverage closure.
IP/SoC Verification
- Develop and enhance UVM-based verification frameworks for PCIe Gen6.
- Validate PCIe Gen6 features including FLIT mode, PAM4 signaling-related checks, Link training, Flow control, LTSSM states, EQ, DLL/PHY interactions.
- Perform formal verification, assertion-based verification, and protocol compliance validation.
- Drive system-level verification, including multi-interface scenarios and performance validation.
Collaboration & Delivery
- Work closely with architects and RTL teams to review microarchitecture and identify corner cases.
- Lead the debug process using waveform analysis, checkers, and assertions.
- Engage with software, validation, and emulation teams for pre-silicon and post-silicon readiness.
- Ensure documentation, reviews, and sign-offs align with project milestones.
Team Mentoring
- Guide and mentor a team of verification engineers.
- Conduct technical training, code reviews, and methodology improvements.
Required Skills & Experience
Core Expertise
- Strong experience (612 yrs) in IP or SoC verification.
- Hands-on expertise in PCIe Gen5/Gen6 protocols; deep understanding of:
- FLIT encoding
- PAM4 / 64 GT/s data rate implications
- LTSSM, TLP/DLLP flows
- Equalization, credit flow, lane margining
- ECN, error injection, protocol corner cases
- Proven experience in UVM, SystemVerilog, OVM/VMM is a plus.
Verification Technical Skills
- UVM testbench architecture & development
- Constrained-random verification
- Functional coverage & code coverage closure
- Assertion and formal verification (SVA, Jasper, VC Formal)
- Scoreboarding, checkers, protocol monitors
- Strong debug skills (SimVision, Verdi, DVE)
Tools & Flows
- VCS/Questa/Xcelium simulators
- PCIe VIP usage & customization
- Familiarity with Python/Perl/TCL scripting
- Knowledge of emulation, FPGA prototyping is a plus
Preferred Qualifications
- Experience leading medium-to-large verification teams.
- Prior involvement in pre-silicon to post-silicon validation cycles.
- Exposure to other high-speed interfaces (CXL, USB4, DDR5, Ethernet).
- Master's/Bachelor's degree in ECE/EE/CS or equivalent.
What We Offer
- Opportunity to contribute to cutting-edge PCIe Gen6 and next-gen SoC architectures.
- Leadership role with technical ownership and mentoring opportunities.
- Competitive compensation and growth in a world-class semiconductor environment.
About Us:
Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we're committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.
Website
https://www.siliconpatterns.com
