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Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage
Job ID: 142921915
Skills:
Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC
Skills:
Ide, Verilog, System Verilog, Pcie, Scripting, ASIC, Synthesis, Uvm, LINT, RTL, cdc, CXL, Genus
Skills:
Ide, Verilog, System Verilog, Pcie, Scripting, ASIC, Synthesis, Uvm, LINT, RTL, cdc, CXL, Genus
Skills:
power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation