Lead Design Engineer

FPGA Design, C, Schematic design, Pcie, Ethernet, Python, Verilog RTL coding, Analyzers, Oscilloscopes, High speed SERDES, UCIe, Debug skills, Bit Error Rate Testers, IP SoC Physical Layer Electrical Validation, CXL, Protocol Exercisers, Post-Silicon PHY Systems Interop and Compliance testing

C Programming Language, Tcl Scripting, Embedded programming languages, Waveform viewers, Low level APIs on Microcontrollers, Simulators, Verification EDA Tools, Bare-metal programming

SystemVerilog Assertions (SVA), Verilog, Computer Architecture, systemverilog, Uvm, Digital Design, Micro-architecture, Rtl Design, Design Verification

power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation

Cadence tool experience, jitter and signal equalization techniques, Phase Interpolator, layout and physical verification, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES