Lead Design Engineer

Verilog, Usb, Pcie, RTL Coding, systemverilog, Datapath design, FIFO design, Microarchitecture, SERDES, MIPI D-PHY

Qt Framework, Linux, Windows For Workgroups, requirement engineering, Ethernet communication protocols, IEC 50128, UI design for rail vehicles, TRDP, IEC 61131, IEC 61375

closure , code coverage , Test Plan Creation, Verilog, Usb, UVM methodology, Mixed-mode simulations, Functional Verification, Emulation, SERDES, GLS debug skills, Automotive IP verification, Assertions development, SV, UCIe, Functional coverage, Analog models, Fault injection, Verification environment planning, Digital verification, Power-aware RTL set-up, Gate-level simulations, Simulation and debug, Constraint randomization, formal verification, HVL, DPHY

Knowledge of rail onboard subsystems for signalling and rolling stock, PSD design, System specification and requirements understanding, Electro-Mechanical Engineering, System engineering methodology, Subcontractor management, PSD project management, Mechanical Engineering

power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation