C Programming Language, Tcl Scripting, Embedded programming languages, Waveform viewers, Low level APIs on Microcontrollers, Simulators, Verification EDA Tools, Bare-metal programming

SystemVerilog Assertions (SVA), Verilog, Computer Architecture, systemverilog, Uvm, Digital Design, Micro-architecture, Rtl Design, Design Verification

power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation

Cadence tool experience, jitter and signal equalization techniques, Phase Interpolator, layout and physical verification, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES

code coverage , closure , Usb, Test Plan Creation, Verilog, Assertions development, formal verification, Functional coverage, UCIe, Power-aware RTL set-up, SV, Gate-level simulations, Emulation, Fault injection, HVL, Constraint randomization, Automotive IP verification, Analog models, DPHY, UVM methodology, Mixed-mode simulations, Digital verification, Verification environment planning, Functional Verification, GLS debug skills, Simulation and debug, SERDES

Sdlc, Agile Methodologies, C, Java, Soc Architecture, Verilog, Python, Git, RTL integration, HDLs, Verification Tools, digital design principles, ASIC Design, VHDL, DevOps practices

Matlab, Device physics and process technologies, Simplis, IC system partitioning and architectural tradeoff analysis, Physical layout management, Analog Circuit Design, Spectre, Post layout parasitic extraction and simulation verification

Perl, Shell scripting, Python, Low Power Verification UPF CPF, AMBA AXI AHB APB, USB 2.0 3.x, ARM-based SoCs, SystemVerilog UVM