Excellent work experience in Analog Layout design in advanced node processes
Hands on experience in any or multiple critical blocks such as BGR, LDO, Charge pump, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Current Mirrors, Comparator, Differential Amplifier etc.
Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
Excellent understanding of Analog Layout concepts (e.g. Matching, Electro- migration, Latch-up, Coupling, Cross-talk, IR-drop, Active and Passive parasitic devices etc.
Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout.
Work closely with the verification team to address layout-related issues and ensure design robustness.
Follow design rules, guidelines, and best practices to ensure design manufacturability and yield.
Collaborate with process engineers to understand process requirements and optimize layout designs accordingly.
Conduct layout parasitic extraction and work with the simulation team to validate and optimize design performance.
Participate in design reviews and contribute to overall design improvements.
Stay updated with the latest advancements in analog layout techniques, process technologies, and industry standards
