Layout/Mask Designer

1. TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience.

2. Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.

3. Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience.

4. Responsible for on-time delivery of block-level layouts of acceptable quality.

5. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.

6. BE or MTech in Electronics/VLSI Engineering

7. Good communications skills as we work with cross-functional teams.

8. Share the profiles who have good hands-on experience in recent times on lowers nodes.

9. TM should work independently.

10. 4 to 8 years of experience – flexible

11. If a candidate has HBM experience, it is an added advantage. Analog blocks like Regulators/Charge pumps/Power Management etc.