Layout Engineer

Job Title:

Memory Layout Engineer

Location :Bangalore

Experience Required:

3–5 years in custom layout design of memory circuits (SRAM, eDRAM, ROM, Register Files, CAM, or emerging memories).

Job Summary:

We are seeking a Memory Layout Engineer with strong expertise in custom layout design of memory macros at advanced technology nodes. The candidate will be responsible for creating high-quality, DRC/LVS clean layouts, ensuring matching, density, reliability, and performance optimization, and working closely with circuit design and verification teams to deliver robust memory IPs.

Key Responsibilities:

• Develop full-custom layout for memory circuits (SRAM, ROM, Register File, CAM, etc.) at block and macro levels.
• Perform floorplanning, placement, routing, and optimization for area, performance, and power.
• Ensure DRC, LVS, ERC, and antenna-clean layouts across different process corners.
• Implement matching techniques, shielding, dummy structures, and guard rings for robust design.
• Work on memory bitcell arrays, periphery circuits, sense amplifiers, decoders, and write drivers.
• Perform parasitic extraction (PEX) and layout-dependent effect (LDE) analysis.
• Collaborate with circuit designers, verification engineers, and CAD teams for integration and validation.
• Support signoff and tapeout with foundry-specific requirements.
• Automate layout generation or checks using SKILL, Python, or TCL scripting (if applicable).

Required Skills & Qualifications:

• 3–5 years of hands-on experience in custom layout of memory IPs.
• Proficiency in EDA tools (Cadence Virtuoso, Synopsys Custom Compiler, Mentor Graphics).
• Strong knowledge of advanced CMOS processes (28nm, 16nm, 7nm, FinFET, etc.).
• Experience in layout methodologies for high-density and high-performance memory arrays.
• Solid understanding of DRC/LVS/ERC/ANT/PEX signoff flows.
• Knowledge of parasitics impact on memory performance.
• Familiarity with reliability requirements (electromigration, IR drop, ESD).
• Good problem-solving and debugging skills.

Preferred Skills:

• Exposure to SRAM compilers or memory automation flows.
• Knowledge of low-power design techniques in memories.
• Experience with EM/IR analysis tools.
• Familiarity with yield and variability considerations in memory design.

Educational Qualification:

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related fields.