Alternate Job Titles:
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology and a commitment to precision. You thrive in collaborative environments, working closely with global teams and engaging in circuit-layout interaction across various technology nodes. Your strong understanding of IC layout fundamentals, foundry design rules, and semiconductor device physics sets you apart. You possess a solid foundation in CMOS technology and digital design principles, and you're eager to develop your expertise further.
Your hands-on experience with industry-standard EDA tools, such as Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre, gives you the practical skills needed to deliver high-quality layouts. You have worked with multiple foundries including TSMC, Samsung, UMC, and GlobalFoundries, and understand the nuances of their PDKs. Proficiency in scripting languages like Unix/Shell, Python, TCL, Perl, or SKILL allows you to automate and streamline complex workflows, increasing efficiency and reliability.
You are detail-oriented, analytical, and methodical in your approach to problem-solving. Your communication skills, both written and verbal, enable you to engage effectively with peers, stakeholders, and cross-functional teams. You are proactive, eager to learn, and passionate about contributing to innovative projects that push technological boundaries. With a strong sense of responsibility, you take ownership of your work, ensuring timely and high-quality deliverables. Your adaptability and openness to feedback make you a valuable team member, ready to help Synopsys maintain its leadership in the semiconductor industry.
What You'll Be Doing:
- Designing and developing a wide range of standard cell layouts, from simple inverters and NAND/NOR gates to more complex structures such as AOI, OAI, multiplexers, level shifters, flip flops, and multi-bit cells within the Logic Libraries IP team.
- Implementing standard cells using planar, CMOS, FinFet, GAA, uni-directional, and multi-directional routing technologies, including the latest cutting-edge process nodes.
- Performing and analyzing sign-off checks (DRC/LVS/ERC/ANT/DFM) to ensure full compliance with foundry rules, optimizing manufacturability, performance, and yield across various foundries.
- Collaborating with global teams, including circuit design, CAD, and physical design groups, to resolve design and methodology issues, and to implement and optimize layout designs.
- Leading and participating in design reviews, providing critical feedback to improve overall quality, manufacturability, and performance of standard cell libraries.
- Employing Unix/Shell/Python/TCL/ICV scripting to automate and enhance design workflows, enforce QA checklists, and generate quality metrics for continuous improvement.
The Impact You Will Have:
- Enable the creation of high-quality, manufacturable standard cell libraries that form the foundation of advanced semiconductor products worldwide.
- Drive innovation by leveraging the latest process technologies and design methodologies to deliver world-class IP solutions.
- Enhance productivity and efficiency through automation of critical design and verification workflows.
- Ensure rigorous compliance with foundry rules, directly impacting yield, reliability, and performance of silicon chips.
- Foster a culture of collaboration and knowledge sharing across global teams, elevating the quality and capabilities of the entire organization
- Contribute to the continuous improvement of design processes, methodologies, and tools, maintaining Synopsys leadership in the industry.
What You'll Need:
- Bachelor's degree with a minimum of 5 years, or advanced degree with at least 3 years, of experience in standard cell or logic library layout development.
- Proficiency with EDA tools such as Synopsys Custom Compiler/Virtuoso, Innovus/ICC2, and ICV/Calibre for DRC/LVS/DFM sign-off.
- Hands-on experience with PDKs from leading foundries (TSMC, Samsung, UMC, GlobalFoundries).
- Strong scripting skills in Python, Tcl, Perl, SKILL, and shell scripting for workflow automation.
- In-depth understanding of CMOS, double patterning technology (DPT), electromigration/IR drop (EM/IR), ESD/latch-up, noise, and digital layout fundamentals.
Who You Are:
- Highly analytical, detail-oriented, and quality-focused.
- Excellent communicator with strong written and verbal English skills.
- Collaborative team player, adept at working in cross-functional, global teams.
- Self-driven, able to work independently and manage multiple priorities.
- Adaptable and open to feedback, with a growth mindset and willingness to learn.
The Team You'll Be A Part Of:
You will be part of a dynamic, innovative, and high-performing globally distributed Logic Library layout design team. The team is focused on creating world-class IP solutions and is dedicated to technical excellence, continuous improvement, and collaborative problem-solving. Together, you will push the boundaries of what's possible in standard cell and logic library design, supporting the next generation of semiconductor products.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
