- Lead and execute Analog Mixed-Signal layout design for high-speed DDR/HBM IPs
- Deliver robust and high-quality physical layout designs ensuring adherence to DDR/HBM specs
- Apply deep understanding of FinFET and CMOS technology at 28nm and below
- Handle high-speed digital layout verification with attention to signal integrity
- Implement advanced floorplanning techniques and apply submicron mitigation strategies
- Coordinate with remote layout teams globally for layout quality and deliverables
- Drive internal flow adherence for tape-out readiness and schedule compliance
- Collaborate with PHY designers, package engineers, and system teams to meet design objectives
- Oversee IO layout requirements including bondpads, ESD, IR/EM, and DFM considerations
- Utilize physical verification tools and support Place & Route and top-level verification flows
The Impact You Will Have:
- Shape next-gen high-speed memory interface solutions through expert physical design
- Ensure quality layout execution in advanced nodes, directly impacting performance and reliability
- Drive project delivery across global teams with technical leadership and coordination
- Enable Synopsys to meet customer demand in high-speed memory IPs with quality and timeliness
- Reinforce design flow adherence and process discipline to ensure tape-out success
- Contribute to the robustness of global layout practices through review and mentorship
What You'll Need:
- 612 years of experience in Analog Mixed-Signal layout, specifically with DDR/HBM IPs
- Expertise in FinFET and CMOS layout at 28nm and below
- Strong knowledge of signal integrity, DRC/LVS/LPE, ESD/latchup, and IO pitch/layout constraints
- Familiarity with ASIC physical design flows including LEF, Place & Route, and verification
- Hands-on experience with advanced layout tools and scripting (Perl, TCL, etc. preferred)
- Proven leadership in global coordination and layout delivery
- Excellent communication and customer interaction skills
