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Job ID: 141359095
Skills:
Perl, Verilog, Python, Tcl, Synopsys VCS, Mentor Questa, VHDL, Cadence Xcelium, Uvm, systemverilog
Skills:
C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools
Skills:
C, Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools
Skills:
C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, TLM
Skills:
Perl, Python, constraint-random tests, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog
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