Job Title: IP Design Verification Engineer
Experience: 7 15 Years
Location: Bangalore
Job Overview
We are looking for an experienced
IP Design Verification (IP DV) Engineer with strong expertise in SystemVerilog/UVM-based verification of high-speed IPs and interconnect protocols. The ideal candidate should have hands-on experience in building scalable verification environments, coverage closure, and working in a multi-national setup.
Key Responsibilities
- Develop and execute verification plans for complex IPs.
- Build reusable verification environments using SystemVerilog (SV) / UVM.
- Perform IP verification for high-speed serial and interconnect protocols.
- Drive coverage closure including:
- Code Coverage
- Functional Coverage
- Toggle Coverage
- Create and maintain technical documentation:
- Testbench Specification
- Test Plan Specification
- Collaborate with cross-functional and global teams to ensure high-quality IP delivery.
Required Technical Skills
Verification Methodology:
- Strong expertise in SystemVerilog (SV) and UVM
- IP-level verification experience (6+ years minimum in IP DV)
Interconnect Protocols (Experience In One Or More)
- DDR
- PCIe
- MIPI
- USB
- Ethernet
- CXL
- UCIe
- UFS
High-Speed Serial Interfaces (Hands-on Experience In At Least One)
- PCIe
- UCIe
- USB
- Ethernet
- DDR
- UPF
Tools
- Synopsys VCS
- Cadence Incisive
Scripting Skills (Good Exposure Required)
Soft Skills & Other Requirements
- Exposure to working in a multi-national/global environment.
- Excellent oral and written communication skills.
- Strong analytical and debugging skills.
- Adaptability, flexibility, and willingness to learn.
- Ability to work independently and within cross-functional teams.
