
IO and Mixed Signal Layout Design Engineer

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Job ID: 151999973
Skills:
layout verification , Ant, PERC, LPE, AI automation in layout, LEF generation, Cadence Virtuoso Layout suite, Siemens CALIBRE verification tools, SKILL Programming, EM, Analog Mixed-signal IP development, Ir, LVS, Dfm, PNR, Physical Design flow, ERC, DRC, Script Programming, FinFET layouts