Intern-Semico
Intern-Semico
Quest GlobalThis job is no longer accepting applications
Job Description
Job Requirements
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Key Responsibilities
Technical Skills
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Key Responsibilities
- Perform floorplanning, placement, clock tree synthesis (CTS), and routing
- Handle timing closure (STA) including setup and hold fixes
- Work on power optimization and IR drop analysis
- Perform physical verification (DRC, LVS, ERC)
- Execute ECO implementation and convergence
- Collaborate with RTL, DFT, and STA teams for design closure
- Analyze and fix congestion, signal integrity, and noise issues
- Ensure design meets foundry and sign-off requirements
Technical Skills
- Strong understanding of ASIC/SoC design flow
- Hands-on experience in:
- Floorplanning & Placement
- CTS & Routing
- Static Timing Analysis (STA)
- Power analysis (IR/EM)
- Good knowledge of:
- Process technologies (7nm / 14nm / 28nm etc.)
- Signal integrity & crosstalk
- Scripting skills:
- Tcl / Python / Shell
- Synopsys (ICC2, PrimeTime, Fusion Compiler)
- Cadence (Innovus, Tempus, Voltus)
- Mentor Graphics tools (Calibre DRC/LVS)
- Bachelor's or Master's degree in Electronics / VLSI / Electrical Engineering
- 2–10 years of experience in physical design (based on seniority)
- Experience in advanced nodes (≤16nm)
- Knowledge of low-power design techniques (UPF/CPF)
- Exposure to DFT and chip-level integration
- Experience in multiple tape-outs
- Timing closure (setup/hold violations)
- Power and area optimization
- Design rule clean (DRC/LVS clean)
- On-time project delivery
- Quality of tape-out
More Info
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Key Skills
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