Bachelors degree in Electrical Engineering or related degree and 8+ years related experience or Masters degree in Electrical Engineering or related degree and 6+ years related experience
6 + years of experience writing and debugging complex test benches
Must have deep understand of all aspects of Verification from building Testbenches, developing Test plans and pseudo-random tests, Functional coverage.
Must have proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM
Should have exceptionally good command over fundamental OOP principles.
A good understanding of a complex protocol like PCIe or other multi-layered protocol
