IBM Processor Architecture and Logic design Engineer

Your Responsibilities

• Microarchitecture design and development of features.
• Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive
• Performing timing closure and CDC (Clock Domain Crossing) analysis.
• Designing power-efficient logic.
• Participating in Agile project planning and execution.
• Applying your demonstrated experience in the microarchitecture and design of state-of-the-art processor features to enhance high-performance secure system performance.

Education

• Required Education: Bachelor's Degree
• Preferred Education: Master's Degree

Required Technical and Professional Expertise

• 4+ years of relevant experience.
• At least one generation of processor L2 cache or LLC design delivery leadership.
• Expertise in cache coherence protocols for symmetric multiprocessors (SMP), including both chip SMP and multi-socket SMP.
• Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations.
• Working knowledge of memory consistency, store ordering, and weakly and strongly ordered memory.
• Experience in the logical and physical design of caches, covering:
• Directories (tags, set associative memories)
• Data SRAM
• Design for low latency
• Multiple parallel finite state machine design
• Deadlock-free designs