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High-speed Analog Layout engineer

High-speed Analog Layout engineer

IBM
6-8 Years
Not Disclosed
Early Applicant
  • Posted a day ago
  • Be among the first 10 applicants

Job Description

Introduction

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

Your Role And Responsibilities

As a Hardware Developer you will design, verify, and deliver highspeed serdes layouts for Power & Z server processors and ASICs using the latest technologies.

Responsibilities

  • Responsible for layout design of assigned blocks with Cadence Virtuoso XL/VXL/MXL features.
  • Responsible for cleaning LVS, DRC, Antenna, and methodology checks.
  • Responsible for fixing various reliability issues EMIR, ESD/Latchup.
  • Should apply standard layout practices such as Layout matching, parasitic, noise & noise isolation, supply consideration, latch up, shielding, Well's substrates and Isolation.
  • Should have strong collaboration with Analog Designers across the globe to solve challenging problems.

Preferred Education

Bachelor's Degree

Required Technical And Professional Expertise

  • MS Degree in Electrical/Electronic Engineering or equivalent with 6+ years of relevant experience.
  • Experience in high-speed layout design of Transmitter, receiver, PLL, clocking, PI, Bandgap and voltage regulators would be an added benefit.
  • Should have layout experience in 2nm GAAFET, 5/7nm FINFET nodes
  • Strong knowledge of double patterning, device matching, signal shielding, layout parasitic and layout dependent effects.
  • Strong fundamental knowledge in semiconductor device physics, cross-section, and construction.
  • Knowledge of skill/Perl/tcl scripting is desirable.
  • Should be a good team player and self-motivated.

Preferred Technical And Professional Experience

  • Advanced VLSI Design Tools: Exposure to specialized VLSI design tools and software, including those used for creating and manipulating physical shapes for complex circuit designs.
  • Semiconductor Process Knowledge: Familiarity with semiconductor processes and their impact on circuit design and layout, including understanding of semiconductor ground rules.
  • Circuit Simulation Techniques: Experience with circuit simulation techniques and tools used to validate the logical function of circuits and ensure design integrity.

More Info

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Industry:
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Key Skills

Layout dependent effects

Signal shielding

Semiconductor device physics

Cadence Virtuoso XL VXL MXL

Parasitic noise

Noise isolation

Supply consideration

Latch up shielding

Well’s substrates

Skill Perl tcl scripting

Layout matching

Double patterning

Device matching

2nm GAAFET

About Company