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GPU Physical Design Engineer (Sr Lead/Staff)

3-8 Years
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Job Description

Key Responsibilities

  • Execute full physical design flow for high-performance, low-power GPU cores, including floorplanning, placement & routing (PnR), clock tree synthesis (CTS), power planning, IR drop analysis, signal integrity, and timing closure.
  • Perform multi-mode, multi-corner (MMMC) timing analysis and fix violations, implement ECOs, and ensure functional and design-for-test (DFT) constraints are met.
  • Collaborate closely with design, DFT, and place-and-route teams to resolve constraint validation, verification, and physical design issues.
  • Drive timing convergence and power, performance, and area (PPA) trade-offs in data-path intensive cores.
  • Conduct formal and physical verification including DRC/LVS checks and power distribution network (PDN) analysis.
  • Develop and maintain automated flows using scripting languages (Perl, Tcl) and shell scripting in Linux/Unix environments.
  • Deliver physical design solutions aligned with project milestones while working collaboratively in a multi-engineer team.


Minimum Qualifications

  • Bachelor's degree or higher in Electrical/Electronics Engineering, Computer Science, or a related field.
  • 4+ years of hardware engineering experience for Bachelor's degree holders, or 3+ years for Master's degree holders, or 2+ years for PhDs.
  • Strong expertise with industry-standard physical design tools such as Synopsys ICC2, Cadence Innovus, PTSI, and Tempus in advanced technology nodes.
  • Proven experience in physical implementation of high-performance GPU or similar complex cores, including timing closure and power optimization.
  • Deep understanding of clocking architectures and advanced static timing analysis (STA).
  • Proficiency in scripting languages (Perl, Tcl) and Linux/Unix shell scripting.
  • Demonstrated ability to work effectively in team environments under project deadlines.
  • Excellent problem-solving and communication skills.


Preferred Qualifications

  • 8+ years of experience in physical design/implementation.
  • Prior experience working on GPU or high-speed digital cores.
  • Hands-on experience with formal verification and physical verification flows.

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About Company

QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.

Job ID: 115166377