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GLS Verification Engineer
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GLS Verification Engineer
Proxelera Private LimitedThis job is no longer accepting applications
Job Description
Key Responsibilities:
- Develop and execute gate-level simulations (GLS) for IP and SoC verification.
- Implement verification environments using SystemVerilog and Universal Verification Methodology (UVM).
- Write and validate SystemVerilog Assertions (SVA) to ensure functional correctness.
- Collaborate with design teams to understand specifications and develop test plans.
- Conduct coverage-driven constrained random validation to ensure thorough verification.
- Perform functional verification for AMBA standard interfaces including AXI, AHB, APB, and OCP.
- Use scripting tools for automation of verification tasks and regression testing.
- Debug and resolve functional issues identified during verification cycles.
- Maintain detailed documentation of verification plans, test results, and bug reports
More Info
Job Type:
Industry:
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Key Skills
SystemVerilog Assertions
About Company
Proxelera is your premier outsourced product development partner (OPD), specializing in Semiconductors, Systems, and Bespoke Hardware. Proxelera combines process rigour with advanced technical expertise to deliver transformative solutions while fostering industry-academia collaboration and VLSI talent development.
Skills:
Vcs, Perl, Python, Tcl, Sta, Verdi, Gate-Level Simulation, reset clock-domain issues, RTL-to-netlist flow, Timing Concepts, Uvm, systemverilog, SDF annotation, X-propagation
Skills:
Verilog, Synopsys VCS, Cadence Xcelium, SDF annotation timing checks, Recovery removal checks, Setup hold analysis, Modelsim, Post-synthesis and post-layout netlist verification, systemverilog, Siemens QuestaSim