GLS Verification Engineer

Key Responsibilities:

• Develop and execute gate-level simulations (GLS) for IP and SoC verification.
• Implement verification environments using SystemVerilog and Universal Verification Methodology (UVM).
• Write and validate SystemVerilog Assertions (SVA) to ensure functional correctness.
• Collaborate with design teams to understand specifications and develop test plans.
• Conduct coverage-driven constrained random validation to ensure thorough verification.
• Perform functional verification for AMBA standard interfaces including AXI, AHB, APB, and OCP.
• Use scripting tools for automation of verification tasks and regression testing.
• Debug and resolve functional issues identified during verification cycles.
• Maintain detailed documentation of verification plans, test results, and bug reports