GLS Verfication Engineer | 2+ Years

We're looking for an experienced GLS Verification Engineer with 5+ years of hands-on experience in Gate-Level Simulation and ASIC/SoC verification.

Key Responsibilities

• Execute Gate-Level Simulation (GLS) using post-synthesis/post-P&R netlists.
• Perform RTL-to-Gate correlation and debug functional mismatches.
• Work with SDF back-annotation, timing violations, X-propagation, reset and clock issues.
• Debug GLS failures using VCS/Verdi, Xcelium/SimVision or equivalent tools.
• Collaborate with RTL, DV, STA, DFT, Synthesis and Physical Design teams.
• Develop GLS regression and debug automation using Python/Tcl/Shell.

Must Have

• 5+ years in GLS / ASIC / SoC Verification
• Strong Verilog/SystemVerilog
• Hands-on SDF, timing simulation and netlist debugging
• Experience with VCS/Verdi or Xcelium
• Strong Linux and scripting skills

Good to Have

• STA / PrimeTime
• DFT / Scan GLS
• UPF / Low-Power GLS
• Post-P&R signoff experience

Bengaluru | Hybrid | Full-time

Keywords: GLS | Gate-Level Simulation | SDF | ASIC | SoC | Verilog | SystemVerilog | VCS | Verdi | Xcelium | STA | DFT