Develop all aspects of RTL2GDS for ASIC/Mixed signal chips.
Complete ownership of physical design integration and CAD flow for Mixed signal chip development.
Drive the closure of timing and power/Physical convergence of the design.
Contribute to physical design methodologies and automation scripts for various implementation steps.
Define and implement innovative schemes to improve Performance, Power, Area (PPA) and CAD methodology.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in ASIC physical design flows and methodologies in advanced process nodes.
Experience in synthesis, Place and route (PnR), sign-off convergence including Static timing analysis (STA), PDN, electrical checks, and physical verification.
Preferred qualifications:
Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience.
10 years of experience in ASIC Physical design/flow development/automation.
Experience in analog mixed signal design/CAD automation/Physical integration.
