THE ROLE:
As a member of the Strategic Silicon Solution Group Full Chip Low Power Design and Signoff team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success.
THE PERSON:
A successful candidate should have minimum 8 to 15 years approximate work experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power design/signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBLITIES:
- Expertise in Full Chip Power Delivery Network Design, Implementation and Signoff
- Must have good understanding of RDL & Power grid design.
- Must know the NPV Static, Dynamic & SEM Run.
- Must have good experience of Vectored dynamic, CPM & Ramp up time analysis and current analysis.
- Must have experience on Full chip, Sub-system level & tile/block/partition level EMIR analysis and signoff
- Should have good knowledge of package level EMIR analysis.
- Expertise in low power design and implementation such as clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption.
- Should have good knowledge on simulation of special cell's with target power analysis.
- Should possess good knowledge of Power switch insertion, Secondary PG design towards improvising PPA.
- Mentor/coach/guide design engineers to achieve the project goal.
- Should have hands on experience on tools like Redhawk-SC, ICC2 & Prime Time or equivalent industry standard tools.
- Should have good scripting experience in Shell, Python, Perl, TCL, UNIX
PREFERRED EXPERIENCE:
- Understanding of ICC2 or Fusion Compiler Physical Design flows/methodologies or equivalent tools. Expertise on tool expected.
- Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts.
- Experience with RHSC, PTPX, ICC2, Fusion Compiler
- Experience with mentoring a team on lower tech node (5/3nm) projects on PDN (EMIR)
- Experience in Full Chip/Sub-system level Physical Verification including DRC, LVS, DFM, ESD, High voltage checks etc,
ACADEMIC CREDENTIALS:
- Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
