Job Title: Front-End Lead Engineer (ASIC / RTL / Functional ECO)
Location: Bengaluru (Bangalore), India
Department: Silicon Design Engineering / RTL Design
Employment Type: Full-time
Experience: 68 years (Lead Engineer)
Notice Period: Immediate / 1530 days preferred
Role Overview
We are hiring a
Front-End Lead Engineer to drive
RTL/IP development and front-end signoff, with strong ownership of
Functional ECO implementation at gate-level netlist. This role requires hands-on expertise across the ASIC front-end flow, strong collaboration with verification and physical design teams, and the ability to mentor engineers while delivering high-quality signoff-ready designs.
Key Responsibilities
- Front-End Design & Signoff
- Lead front-end development of digital IP blocks / subsystems from concept through implementation.
- Drive design signoff checks: lint, CDC/RDC, synthesis readiness, STA constraints, and timing convergence support.
- Partner with architecture, verification, physical design, firmware/software, and program teams to close design requirements.
- Support P&R and signoff teams with RTL fixes, constraints updates, and ECO requirements.
- Functional ECO Leadership (Netlist-Level)
- Analyze RTL deltas and define minimal gate-level modifications for Functional ECOs.
- Perform gate-level netlist edits manually and/or via ECO automation tools.
- Execute and review ECO flows using Synopsys Formality ECO and/or Cadence Conformal ECO.
- Ensure robust validation using formal equivalence checking and simulation for ECO changes.
- Coordinate ECO integration across RTL, synthesis, verification, and PD teams.
- Maintain ECO documentation including change logs, methodology notes, and audit trails.
- Team & Project Leadership
- Own schedules, deliverables, and quality for front-end execution items.
- Mentor engineers on RTL design, signoff checks, ECO methodology, debugging, and closure practices.
- Drive improvements in front-end methodology, automation, and best practices.
- Identify ECO risks early and work with stakeholders on mitigation and timelines.
Required Qualifications
- 68 years of hands-on experience in ASIC front-end design (RTL-to-synthesis/signoff support).
- Strong Functional ECO expertise using Formality ECO and/or Conformal ECO.
- Proficiency in Verilog/SystemVerilog, gate-level netlist understanding, and scripting (Tcl / Perl / Python).
- Working knowledge of STA constraints and front-end / physical design interactions.
- Strong foundation in formal verification, simulation, debugging, and closure.
- Strong analytical skills, attention to detail, and ownership mindset.
Education: B.E./B.Tech or M.E./M.Tech in Electrical/Electronics or related.
Added Advantage: Experience in AMD-like environments / flows (preferred, not mandatory).
What Success Looks Like
- ECO changes implemented with minimal, correct netlist edits and clean validation (formal + sim).
- Signoff issues (lint/CDC/RDC/constraints/timing convergence support) driven to closure with strong quality.
- Effective cross-team coordination and clear ECO documentation.
