FPGA Verification Engineer
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Responsibilities:
Test bench design and implementation.
Test coverage plan definition.
Constrained random test development.
Coverage specification analysis.
Automation of the regression test suite
Desired technical skills:
Proficiency in OOPs, Verilog System Verilog.
Solid verification skills : planning, problem solving, debug, adversarial testing and random testing.
Project based work experience with UVM/VMM methodologies.
Candidate must have experience with architecting the testplan test bench.
Hands on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART etc..
Job ID: 109148519
Skills:
Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero
Skills:
Doors, Tcl Scripting, FPGA Synthesis Place and Route, DO-254 development process, RTL development using VHDL, Hardware system design knowledge of digital logic, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, FPGA design tools like Libero, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory
Skills:
code coverage , Regression Testing, Ethernet Protocols, Python, perl, Ovm, systemverilog, Uvm, functional coverage, X-propagation, multiple RTL simulators
