FPGA RTL Design & Emulation Engineer

FPGA RTL Design & Emulation Engineer (5-10 Yrs) – Bengaluru

Role:

Looking for an FPGA RTL Design & Emulation Engineer with 5 years of experience in RTL development, FPGA prototyping, and pre-silicon validation.

Key Skills:

• Verilog / SystemVerilog (RTL Design)
• FPGA design flow (Synthesis, STA, CDC, Timing Closure)
• Emulation platforms (ZEBU or similar)
• FPGA bring-up & hardware debugging
• Python / TCL / Shell scripting
• Protocols: I2C, SPI, UART, PCIe

Responsibilities:

• Develop RTL and build FPGA/emulation models
• Perform synthesis, timing analysis, and IP integration
• Work on emulation, validation, and debugging
• Collaborate with verification teams for simulation & regression

Location: Bengaluru