
Search by job, company or skills
Job ID: 148512131
Skills:
Fpga, Tcl, FPGA Lead Engineer, Xilinx
Skills:
Static Timing Analysis, FPGA Design, Timing Closure, Synthesis, Code coverage analysis, RTL design using Verilog, Digital ASIC FPGA architectural design, Optimization, systemverilog
Skills:
Vcs, Debugging, Digital Signal Processing, Tcl, FPGA Design, Python, Perl, Modelsim, Questa, Uvm, wireless communication standards, systemverilog, Vivado, AMD Zynq RFSoC devices, Synopsys DC, Sta, high-speed packet processing, VHDL, Implementation, upper layer protocol implementation, Synthesis, Altera Agilex devices, Timing Closure, spyglass
Skills:
Ovm, Pcie, Ethernet, System Verilog, IPSEC protocols, Uvm, FPGA prototyping, FPGA architecture, formal verification, MACSEC, constrained random verification methodologies, Pre Silicon Validation Verification
Skills:
Python, Pcie, Questasim simulation, AXI4, TCL scripts, SV-UVM, ARINC standards, UVM environments, DO-254
We don’t charge any money for job offers