Job Description
About the Role
We are a proprietary trading and quantitative research firm operating in Indian and Global equity
and derivatives markets. As an FPGA Engineer, you will own production hardware that sits
between us and the exchange — market data decoders, order execution paths, and signal
computation pipelines where every nanosecond is measured, attributed, and defended.
You will work directly with the Trading Infra Technology Manager and have visible impact on
PnL from your first deployment.
What You Will Work On
- Architect and own end-to-end FPGA pipelines for NSE TBT / BSE EOBI market data
decoding at line rate
- Design and harden order book engines in Block RAM with deterministic latency
- Build fixed-point signal computation pipelines — micro price, OBI, VWAP, and proprietary
alpha signals — co-designed with the quant research team
- Implement NSE NNF order encoding, pre-trade risk checks, and order-gateway logic in
hardware
- Drive timing closure on Ultrascale+ designs and push wire-to-wire latency below current
benchmarks
- Own the verification stack — testbenches, software reference models, and production
telemetry
Must Have
- 3+ years of production FPGA design experience in a latency-critical or high-reliability
domain
- Deep proficiency in SystemVerilog / Verilog / VHDL — you have shipped designs that run
unattended in production
- Strong grasp of digital design fundamentals: pipelining, CDC, FSMs, timing analysis,
BRAM / DSP slice utilization, and floorplanning
- Hands-on experience with Vivado timing closure on real Ultrascale+ or Virtex-7 designs —
not just synthesis runs
- Proven ability to debug at the waveform level under pressure
- Comfort working in a small, high-ownership team where you set the bar
Good to Have
- Experience with line-rate UDP / TCP, Ethernet MAC/PCS, or 10G/25G/100G networking
on FPGA
- HLS experience — Vivado HLS / Vitis HLS / Intel HLS Compiler — for rapid iteration on
signal pipelines
- Prior exposure to financial market data, exchange protocols (FIX, ITCH, OUCH, NSE
NNF, BSE EOBI), or latency-critical trading systems
- Performance-level C++ for software reference models and host-side tooling
- Published research or open-source contributions in reconfigurable computing, real-time
systems, or hardware acceleration
Required Skills
[Verilog/VHDL]
Additional Information
Must Have
- 3+ years of production FPGA design experience in a latency-critical or high-reliability
domain
- Deep proficiency in SystemVerilog / Verilog / VHDL — you have shipped designs that run
unattended in production
- Strong grasp of digital design fundamentals: pipelining, CDC, FSMs, timing analysis,
BRAM / DSP slice utilization, and floorplanning
- Hands-on experience with Vivado timing closure on real Ultrascale+ or Virtex-7 designs —
not just synthesis runs
- Proven ability to debug at the waveform level under pressure
- Comfort working in a small, high-ownership team where you set the ba
